The invention relates to the fields of standard-cell and mask programmed gate-array integrated circuit design. In particular, the invention relates to a cell design for use in CMOS gate-array integrated circuit design that allows reduced parasitic capacitance of clock-line input interconnect.
Clock line routing delay is a perennial issue in the art of integrated circuit design. It is known that excessive power drain can result from slow rise and fall times of clock lines because common clocked-inverter or multiplexor-based xe2x80x9cflip-flopxe2x80x9d designs can conduct xe2x80x9ccrowbarxe2x80x9d current during slow, delayed, clock edges. It is also known that clock skew, or excessive differences in clock delay, to different flip-flops of a chip can cause logical malfunction because signals may propagate in a different clock cycle than that required by the logical design of the chip.
Signal routing delay, including clock routing delay, on an integrated circuit is largely a function (F) of the distributed resistance (R) of the interconnect distributing the signal and of the distributed load capacitance (C) driven by the signal. Function F is a complex function of the way the R and C is structured, is primarily a function of the product of various components of R and C, and that part of function F is the R-C delay of the routing.
The capacitance C comprises gate capacitance of load devices as well as parasitic capacitances coupling the signal routing to adjacent signal routing, metal interconnect on other layers, the integrated circuit substrate, source and drain regions of devices, and other features on the chip. The resistance R comprises the resistance of connections between layers of the chip and resistance resulting from the sheet resistivity of the interconnect. While sheet resistivity of metal interconnect may be as low as 0.05 ohms per square, a 0.25 micron wide metal line only a quarter of an inch long of 0.05 ohm material presents approximately 1250 ohms resistancexe2x80x94enough to be significant.
It is known that high R-C delays in clock line routing on an integrated circuit can cause slow, delayed, rise and fall times. Further, high R-C delays in clock line routing can cause excessive clock skew. It is therefore desirable to keep R-C delays of clock lines low to ensure that chips will work well.
Many techniques have been used to reduce the amount and effect of clock line R-C delay on integrated circuits. Several techniques must often be combined to produce acceptable results. Common techniques include:
1. distributing multiple clock drivers over the chip while balancing driver sizes, and distribution grid or tree layouts, to equalize delay among the multiple grids and trees that result,
2. use of wider-than-minimum metal for clock distribution to reduce R,
3. connecting clock distribution lines into grid or tree structures to reduce R,
4. driving long, slow, or heavily loaded clock lines at multiple points,
5. use of silicon on insulator technologies to reduce parasitic capacitance,
6. deliberate addition of delay to flip-flop designs to reduce skew sensitivity,
7. local buffering of clock lines at, or internal to, flip-flops to reduce the number of devices driven by the clock lines, thereby reducing load C on the clock lines, and
8. spacing clock lines further from other circuitry than the minimum spacing used elsewhere in the chip.
These techniques require substantial design effort, circuitry, processing expense, layout space, or sacrifice of potential performance. It is therefore desirable to reduce the effect of R-C delay of clock lines in other or additional ways.
Many flip-flop designs used today have multiple clocked inverters, or, equivalently, standard inverters driving through clock-controlled transmission gates. These structures are often coupled in pairs, such that a first clocked inverter is driving while a second inverter of the pair is in a high impedance state; when the clock has an opposite value the first inverter is in high impedance and the second inverter drives. A typical D-type edge-triggered flip-flop design incorporates two such clocked inverter pairs. Other clocked gates, such as clocked NAND, NOR, AND-OR-INVERT, and OR-AND-INVERT gates are often paired with clocked inverters to build other flip-flops, including common types of D-type edge-triggered flip-flops having a reset input.
Masked programmed gate-array integrated circuits are typically built on a master-slice having a regular array of P and N type transistors. A base-cell for such an array is a small portion of such a regular array that may be replicated in the circuit layout to form a larger portion of the array. Because latchup considerations require spacing between adjacent N and P type transistors, these transistors are typically built in rows, where devices in the same row are of the same type; this permits placement of more devices per unit area than possible with other designs. A common design for use with a xe2x80x9csea of gatesxe2x80x9d router alternates pairs of rows of N type devices with pairs of rows of P type devices. Similarly, a common design for use with a channel router has device strips separated by routing channels. Each device strip comprises a row of N type devices adjacent to a row of P type devices.
Standard-cell integrated circuit designs are typically created by first designing a library of standardized designs for performing typical logical functions, each such standardized design is known as a xe2x80x9ccellxe2x80x9d. A logical design of the integrated circuit, or portion thereof, is made that invokes cells of the library; specifying cell types and interconnections between cells. Layout is performed by placing required cells in a chip layout, then interconnecting the cells and any surrounding logic as required by the logical design of the circuit.
Cells of a standard cell library are frequently placed adjacent to other cells of the same library. Each cell must therefore be designed such that placement next to any other cell of the library does not cause unexpected design rule violations (such as spacing violations) or functional problems because of short circuits between portions of the adjacent cells. This is enforced by designing cells according to a set of cell-edge rules. In order to ensure cell-edge rules are met, cell libraries have been designed where the transistors of each cell are fabricated in rows in a regular pattern, with higher-level interconnect defining connections of the transistors. A section of the regular pattern of such devices can also be described as a base-cell.
It is also known that modern dynamic memory devices often have logic in them. For example, memory devices may contain data registers to perform dual-data-rate conversion or on-chip caching functions. Similarly, memory devices are known that have internal refresh address counters and multiplexers, as well as address latches and counters for receiving multiplexed addresses and performing burst-mode read or write operations.
A base-cell layout has been devised that incorporates N-channel devices in P-well, and P-channel devices in N-well, in each row of the base cell. This base cell is suitable for either gate-array or standard-cell design methodology. The base cell has two rows, such that a region of P-channel devices in N-well of the second row is adjacent to the region of N-channel devices in P-well of the first row.
The base-cell is copied and arrayed, with mirrored and flipped copies of the cell, in the gate-array or standard-cell design layout such that the well masks have a checkerboard appearance. This array layout is intended for fabrication in a junction-isolated (not a silicon-on-insulator) integrated circuit fabrication process which may be of the N-Well, P-Well, or Twin-Well type.
This results in a gate array that, while it has fewer total devices per unit area than does a typical row-based gate array, is more convenient for laying out of clocked-gate pairs and multiplexor circuits. Circuits having large quantities of clocked-gate, including clocked inverter pairs, can be laid out into the gate array with less interconnect resistance and capacitance on the clock and not(clock) lines than attained on typical layouts.
Particularly, the base-cell layout of the present invention allows on-chip clock lines to be laid out in a substantially straight, linear arrangement that significantly aids overall device performance and design time to market with only a small increase in the requisite on-chip area, or xe2x80x9creal estatexe2x80x9d.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.